1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device and a method for testing the same.
2. Description of the Related Art
In general a semiconductor memory device such as Dynamic Random Access Memory (DRAM) supports a variety of test items, and a plurality of tests may be performed to secure reliability of the semiconductor memory device.
In the test technology for the semiconductor memory device with more than tens of millions of memory cells, a test time and a screening ability of the test may be main concerns. The test time reduction, in the development period and the mass-production level of the semiconductor memory device, may be directly related to a product fabrication cost. A parallel test (or compress test) is performed to reduce the test time for a plurality of memory cells.
The operation of the parallel test may be performed as follows. First, the same data are written into the plurality of memory cells, and exclusive OR (XOR) logics are then used to read the data from the plurality of memory cells. For example, when the same data are read from the plurality of memory cells, ‘1’ is outputted to determine whether the semiconductor memory device is passed. On the other hand, when different data is read from any one of the plurality of memory cells, ‘0’ is outputted to determine whether the semiconductor memory device is failed. That is, by the parallel test, a large unit of memory cells may be simultaneously screened
Recently, the semiconductor memory device employs a grouped bank structure in which separate global input/output lines are provided for each bank group to improve performance. Therefore, the parallel test suitable for the grouped bank structure is in demand.